1. Field of the Invention
The present invention relates to a apparatus which can be connected to a computer, and more particularly, to a computer connection available data wireless apparatus in which the frequency of a clock signal can be changed.
2. Description of Related Art
It is increasingly made to expand the application field of a computer by connecting a wireless apparatus to the computer, by receiving data to take into the computer and also transmitting data from the computer through a wireless path. For example, a wireless apparatus with a card size is connected to a connector for a memory card which is provided to a notebook-type personal computer and the transfer of data is performed through a wireless path through the same processing as accessing the memory card.
Such a wireless apparatus is disclosed in Japanese Laid Open Patent Disclosure 5-199155 in which the frequency of a clock signal, which defines an operation frequency of each circuit in the wireless apparatus, is changed in accordance with a channel separation in a wireless path used for reception. If the channel separation is narrow, the frequency of the clock signal is lowered so that the channel interference by the harmonic wave of the clock signal is reduced. On the other hand, in a wireless apparatus which can be connected to the computer (to be referred to as a "computer connection available data wireless apparatus" hereinafter), the frequency of the clock signal can be changed in accordance with whether or not a computer is connected, so that the wireless apparatus is operable to follow the operation speed of the computer. When the computer is not connected, the operation frequency of the clock signal is lowered so that reduction of power consumption and noise generation is accomplished. Also, when the computer is connected, the operation frequency of the clock signal is increased such that the wireless apparatus can follow the operation speed of the computer.
FIG. 1 is a diagram schematically illustrating the structure of the computer connection available data wireless apparatus which is conventionally used. The computer connection available data wireless apparatus 101 is composed of a reception antenna 102 for receiving a signal, a reception demodulating circuit 103 for demodulating the received signal, a decoder 104 for decoding the demodulated signal and performing error detection, and a central processing unit (CPU) 105 for performing various control functions. To the central processing unit 105 is connected a read only memory (ROM) 106 in which a program and various fixed data are stored, and a personal computer memory card international association (PCMCIA) controller 107 for performing read and write control of the decoded data and serving as an interface between the computer 110 and the data wireless apparatus. An oscillating circuit 108 for generating a clock signal for the operation of the CPU 105 is connected to the CPU 105 through a counter circuit 109 which divides the clock signal.
The PCMCIA connector 111 to connect the computer connection available data wireless apparatus 101 to the computer 110 and a random access memory (RAM) 112 for storing data to be transmitted or received are connected to the PCMCIA controller 107. The PCMCIA controller 107 is composed of an output buffer 114 of a high drive capability level from which more drive current can be taken out, a control section 113 for performing various controls to read and write the data to be transmitted and received data from and to the RAM 112 through the output buffer, and a connection detecting circuit 115 for detecting whether or not the computer 110 is connected to the PCMCIA connector.
The RAM 112 can be accessed from both of the computer 110 and the CPU 105 through the PCMCIA controller 107. There are cases that the operation speed of the computer is 100 Megahertz (MHz). In order for the CPU 105 to follow such high operation speed, the output buffer 114 of the high drive capability level needs to be employed as a buffer circuit to allow the current quantity to be taken out more. The CPU 105 is capable of operating at a speed in a Mega Hertz range sufficient to handle the signal received by the antenna 102. In order to improve the response to the computer 110, it is desirable to make the CPU 105 operate at higher speed. For this reason, whether or not the computer 110 is connected is detected by the connection detecting circuit 115. When the computer is connected, a frequency division value ratio in the counter circuit 109 is made small such that the high rate clock signal is supplied to the CPU 105. Also, when the computer 110 is not connected, the frequency division value in the counter circuit 109 is made great such that the low rate clock signal is supplied to the CPU 105.
If the frequency of an operation clock signal for the CPU 105 is increased in the state that the computer 110 is connected, the CPU 105 can follow the operation speed of the computer 110. In this case, however, there is a problem of noise generation. As the clock signal frequency is increased, noise is generated and introduced into the receiving antenna and the subsequent receiving circuits, so that an error rate of the received data becomes great, i.e., the reception state becomes wrong. Also, because the parallel data transfer is performed in the computer connection available data wireless apparatus which is conventionally used, about 10 to 30 signal lines are necessary to access the RAM. The power consumption per operation unit frequency of the output buffer of a high drive capability level becomes high, compared to the power consumption of the output buffer of a low drive capability level. Therefore, the power consumption of the data wireless apparatus has becomes high. Moreover, the electric power is wastefully consumed because the output buffer of the high drive capability level, which is provided to make the wireless apparatus follow the operation speed of the computer, is always used even when there is no access from the computer. Especially, In the data wireless apparatus operating with a battery, there is a problem in that the lifetime of the battery has become short due to the high power consumption.